Yesterday at Computex 2021, AMD CEO Lisa Su showed off the company's next big performance playâ3D stacked chiplets, allowing the company to triple the amount of L3 cache on its flagship Zen 3 CPUs.
The technology is just what it sounds likeâa layer of SRAM cache sitting atop the Complex Core Die (CCD) of the CPU itself. Current Zen 3 architecture integrates 32MiB of L3 cache per eight-core chipletâmaking 64MiB total for a 12- or 16-core chiplet like the Ryzen 9 5900X or 5950X. The new technology adds an additional 64MiB L3 cache on top of each chiplet's CCD, bonded with through-silicon vias (TSVs).
The additional 64MiB L3 cache layer does not extend the width of the CCD, resulting in a need for structural silicon to balance pressure from the CPU cooling system. Compute and cache dies are both thinned in the new design, allowing it to share substrate and heat spreader technology with current Ryzen 5000 processors.
Tripling the L3 cache on Ryzen 5000 allows performance gains under some workloadsâparticularly archive compression/decompression and gamingâsimilar to those seen with entire new CPU generations. AMD demonstrated performance uplift via a Gears of War 5 demo. Paired with an unspecified GPU and with clock speed fixed at 4 GHz, a current-model 5900X system achieved 184 fpsâwhile the triple-cached prototype managed 206 fps, a gain of roughly 12 percent.
AMD claims an average of 15 percent improved gaming performance with the new technology, ranging from a low of 4 percent for League of Legends to a high of 25 percent for Monster Hunter: World. This performance improvement requires neither smaller process node nor increased clock speedâwhich is especially interesting, in an era where clock speeds have largely hit a wall, and a physics-determined end to process-node shrink seems to be on the horizon as well.
Anandtech's Ian Cutress notes that AMD's new 3D chiplet stacking process is clearly TSMC's SoIC Chip-on-Wafer technology in action. While AMD isâat least so farâlimiting itself to two layers, TSMC has demonstrated a full 12 layers in action. The problem here is thermalâadding RAM is a near-ideal use of the technology, since the additional silicon doesn't generate much in the way of additional heat. Stacking CPU on CPU would be far more problematic.
AMD states that the redesigned 5900X will enter production later this yearâwell before Zen 4's scheduled launch in 2022. For now, AMD is focusing on the new technology for "high-end Ryzen" CPUs onlyâno mention was made of Epyc, and the additional silicon required for the added cache makes it a likely nonstarter for budget processors, given current materials shortages.
Listing image by AMD
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